TMS320C64x DSP Two Level Internal Memory Reference Guide (Re(19)

Level 1 Data Cache (L1D)

3Level 1 Data Cache (L1D)

The level 1 data cache (L1D) services data accesses from the CPU. The

following sections describe the parameters and operation of the L1D. Theoperation of L1D is controlled by various registers, as described in section 7,Memory System Controls.

3.1L1D Parameters

The L1D is a 16K-byte cache. It is a two-way set associative cache with a

64-byte line size and 128 sets. It also features a 64-bit by 4-entry write buffer

between L1D and the L2 memory.

Physical addresses map onto the cache in a straightforward manner. The

physical address divides into three fields as shown in Figure 3. Bits 5 0 of the

address specify an offset within the line. Bits 12 6 of the address select one

of the 128 sets within the cache. Bits 31 13 of the address serve as the tag

for the line.

Figure 3.

31L1D Address Allocation1312

TagSet Index65Offset0

Because L1D is a two-way cache, each set contains two cache lines, one for

each way. On each access, the L1D compares the tag portion of the address

for the access to the tag information for both lines in the appropriate set. If the

tag matches one of the lines and that line is marked valid, the access is a hit.

If these conditions are not met, the access is a miss. Miss penalties are

discussed in detail under section 3.2.

The L1D is a read-allocate-only cache. This means that new lines are allocated

in L1D for read misses, but not for write misses. For this reason, a 4-entry write

buffer exists between the L1D and L2 caches that captures data from write

misses. The write buffer is enhanced in comparison to the write buffer on the

C621x/C671x devices. The write buffer is described in section 3.2.3.

The L1D implements a least-recently used (LRU) line allocation policy. This

means that on an L1D read miss, the L1D evicts the least-recently read or

written line within a set in order to make room for the incoming data. Note that

invalid lines are always considered least-recently used.

If the selected line is dirty, that is, its contents are updated, then the victim line’s

data is prepared for writeback to L2 as a victim writeback. The actual victim

writeback occurs after the new data is fetched, and then only if the newly

fetched data is considered cacheable. If the newly fetched data is

noncacheable, the victim writeback is cancelled and the victim line remains in

the L1D cache.

SPRU610BTMS320C64x Two-Level Internal Memory19

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