TMS320C64x DSP Two Level Internal Memory Reference Guide (Re(15)

Cache Terms and Definitions

Table 2.

Term

InvalidateTerms and Definitions (Continued)DefinitionThe process of marking valid cache lines as invalid in a particular cache. Alone, this

action discards the contents of the affected cache lines, and does not write back any

updated data. When combined with a writeback, this effectively updates the next

lower level of memory that holds the data, while completely removing the cached

data from the given level of memory. Invalidates combined with writebacks are

referred to as writeback-invalidates, and are commonly used for retaining coherence

between caches.

For set-associative and fully-associative caches, least-recently used allocation refers

to the method used to choose among line frames in a set when allocating space in

the cache. When all of the line frames in the set that the address maps to contain

valid data, the line frame in the set that was read or written the least recently (furthest

back in time) is selected to hold the newly cached data. The selected line frame is

then evicted to make room for the new data.

A cache line is the smallest block of data that the cache operates on. The cache line

is typically much larger than the size of data accesses from the CPU or the next

higher level of memory. For instance, although the CPU may request single bytes

from memory, on a read miss the cache reads an entire line’s worth of data to satisfy

the request.

A location in a cache that holds cached data (one line), an associated tag address,

and status information for the line. The status information can include whether the

line is valid, dirty, and the current state of that line’s LRU.

The size of a single cache line, in bytes.

When a CPU request misses both the first-level and second-level caches, the data is

fetched from the external memory and stored to both the first-level and second-level

cache simultaneously. A cache that stores data and sends that data to the

upper-level cache at the same time is a load-through cache. Using a load-through

cache reduces the stall time compared to a cache that first stores the data in a lower

level and then sends it to the higher-level cache as a second step.Least Recently Used(LRU) allocationLineLine frameLine sizeLoad through

Long-distance accessAccesses made by the CPU to a noncacheable memory. Long-distance accesses

are used when accessing external memory that is not marked as cacheable.

Lower-level memoryIn a hierarchical memory system, lower-level memories are memories that are further

from the CPU. In a C64x system, the lowest level in the hierarchy includes the

system memory below L2 and any memory-mapped peripherals.

Least Recently Used. See least recently used allocation for a description of the LRU

replacement policy. When used alone, LRU usually refers to the status information

that the cache maintains for identifying the least-recently used line in a set. For

example, consider the phrase “accessing a cache line updates the LRU for that line.”LRU

SPRU610BTMS320C64x Two-Level Internal Memory15

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