TMS320C64x DSP Two Level Internal Memory Reference Guide (Re(16)

Cache Terms and Definitions

Table 2.

TermTerms and Definitions (Continued)Definition

Defines what order the effects of memory operations are made visible in memory.

(This is sometimes referred to as consistency.) Strong memory ordering at a given

level in the memory hierarchy indicates it is not possible to observe the effects of

memory accesses in that level of memory in an order different than program order.

Relaxed memory ordering allows the memory hierarchy to make the effects of

memory operations visible in a different order. Note that strong ordering does not

require that the memory system execute memory operations in program order, only

that it makes their effects visible to other requestors in an order consistent withprogram order. Section 8.3 covers the memory ordering assurances that the C64x

memory hierarchy provides.

A cache miss occurs when the data for a requested memory location is not in the

cache. A miss may stall the requestor while the line frame is allocated and data is

fetched from the next lower level of memory. In some cases, such as a CPU write

miss from L1D, it is not strictly necessary to stall the CPU. Cache misses are often

divided into three categories: compulsory misses, conflict misses, and capacity

misses.

The process of servicing a single cache miss is pipelined over several cycles. By

pipelining the miss, it is possible to overlap the processing of several misses, should

many occur back-to-back. The net result is that much of the overhead for the

subsequent misses is hidden, and the incremental stall penalty for the additional

misses is much smaller than that for a single miss taken in isolation.

A read-allocate cache only allocates space in the cache on a read miss. A write miss

does not cause an allocation to occur unless the cache is also a write-allocate cache.

For caches that do not write allocate, the write data would be passed on to the next

lower-level cache.

A collection of line frames in a cache that a single address can potentially reside. A

direct-mapped cache contains one line frame per set, and an N-way set-associative

cache contains N line frames per set. A fully-associative cache has only one set that

contains all of the line frames in the cache.

A set-associative cache contains multiple line frames that each lower-level memory

location can be held in. When allocating room for a new line of data, the selection is

made based on the allocation policy for the cache. The C64x devices employ a least

recently used allocation policy for its set-associative caches.

A method by which a lower-level memory queries a higher-level memory to

determine if the higher-level memory contains data for a given address. The primary

purpose of snoops is to retain coherency, by allowing a lower-level memory to

request updates from a higher-level memory. A snoop operation may trigger a

writeback, or more commonly, a writeback-invalidate. Snoops that trigger

writeback-invalidates are sometimes called snoop-invalidates.Memory orderingMissMiss pipeliningRead allocateSetSet-associativecacheSnoop

16TMS320C64x Two-Level Internal MemorySPRU610B

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