TMS320C64x DSP Two Level Internal Memory Reference Guide (Re(18)

Cache Terms and Definitions

Table 2.

Term

Working setTerms and Definitions (Continued)DefinitionThe working set for a program or algorithm is the total set of data and program code

that is referenced within a particular period of time. It is often useful to consider theworking set on an algorithm-by-algorithm basis when analyzing upper levels of

memory, and on a whole-program basis when analyzing lower levels of memory.

A write-allocate cache allocates space in the cache when a write miss occurs. Space

is allocated according to the cache’s allocation policy (LRU, for example), and the

data for the line is read into the cache from the next lower level of memory. Once the

data is present in the cache, the write is processed. For a writeback cache, only the

current level of memory is updated—the write data is not immediately passed to the

next level of memory.

The process of writing updated data from a valid but dirty cache line to a lower-level

memory. After the writeback occurs, the cache line is considered clean. Unless

paired with an invalidate (as in writeback-invalidate), the line remains valid after a

writeback.

A writeback cache will only modify its own data on a write hit. It will not immediately

send the update to the next lower-level of memory. The data will be written back at

some future point, such as when the cache line is evicted, or when the lower-level

memory snoops the address from the higher-level memory. It is also possible to

directly initiate a writeback for a range of addresses using cache control registers. A

write hit to a writeback cache causes the corresponding line to be marked as

dirty—that is, the line contains updates that have yet to be sent to the lower levels of

memory.

A writeback operation followed by an invalidation. See writeback and invalidate. On

the C64x devices, a writeback-invalidate on a group of cache lines only writes out

data for dirty cache lines, but invalidates the contents of all of the affected cache lines.

Write merging combines multiple independent writes into a single, larger write. This

improves the performance of the memory system by reducing the number of

individual memory accesses it needs to process. For instance, on the C64x device,

the L1D write buffer can merge multiple writes under some circumstances if they are

to the same double-word address. In this example, the result is a larger effective

write-buffer capacity and a lower bandwidth impact on L2.

A write-through cache passes all writes to the lower-level memory. It never contains

updated data that it has not passed on to the lower-level memory. As a result, cache

lines can never be dirty in a write-through cache. The C64x devices do not utilize

write-through caches.Write allocateWritebackWriteback cacheWriteback-invalidateWrite mergingWrite-through cache

18TMS320C64x Two-Level Internal MemorySPRU610B

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