TMS320C64x DSP Two Level Internal Memory Reference Guide (Re(10)

Memory Hierarchy Overview

Table 1.TMS320C621x/C671x/C64x Internal Memory Comparison

TMS320C621x/C671x DSPTMS320C64x DSP

Internal memory structureL1P size

L1P organization

L1P CPU access time

L1P line size

L1P read miss action

L1P read hit action

L1P write miss action

L1P write hit action

L1P → L2 request size

L1P protocol

L1P memory

L1P → L2 single request stall

L1P → L2 minimum cycles between

pipelined misses

L1D size

L1D organization

L1D CPU access time

L1D line size

L1D replacement strategy

L1D banking

L1D read miss action

L1D read hit action

L1D write miss action

L1D write hit action

L1D protocol

L1D → L2 request size

Two Level4 KbytesDirect mapped1 cycle64 bytes1 line allocated in L1PData read from L1PL1P writes not supportedL1P writes not supported2 fetches/L1P lineRead Allocate1 fetch/L1P lineRead Allocate; Pipelined MissesSingle-cycle RAM5 cycles for L2 hitPipelined misses not supported4 Kbytes2-way set associative1 cycle32 bytes64 bytes8 cycles for L2 hit1 cycle16 Kbytes32 bytes16 Kbytes2-way Least Recently Used64-bit-wide dual-ported RAM8 × 32 bit banks1 line allocated in L1DData read from L1DNo allocation in L1D, data sent to L2Data updated in L1D; line marked dirtyRead AllocateRead allocate; Pipelined Misses2 fetches/L1D lineSome C64x devices may not support the 256K cache mode. Refer to the device-specific datasheet.10TMS320C64x Two-Level Internal MemorySPRU610B

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