异步串行接口电路及通信系统设计设计报告(7)

异步串行接口电路及通信系统设计

rdsig<='0'; when \ idle<='1'; dataout(4)<=rx; cnt<=cnt+'1'; rdsig<='0'; when \ idle<='1';

dataout(5)<=rx; cnt<=cnt+'1'; rdsig<='0'; when \ idle<='1';

dataout(6)<=rx; cnt<=cnt+'1'; rdsig<='0'; when \ idle<='1';

dataout(7)<=rx; cnt<=cnt+'1'; rdsig<='1'; when others =>

cnt<=cnt+'1'; end case; else

cnt<='0'; idle<='0';

rdsig<='0'; end if; end if; end process; end one;

uart发送模块 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity dyztx is port(

clk : in std_logic;

datain: in std_logic_vector(7 downto 0);

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异步串行接口电路及通信系统设计

wrsig: in std_logic; idle: out std_logic; tx: out std_logic ); end dyztx;

architecture one of dyztx is signal send:std_logic; signal wrsigbuf:std_logic; signal idlereg:std_logic; signal wrsigrise:std_logic;

signal cnt:std_logic_vector(7 downto 0); begin

idle<=idlereg; process(clk) begin

if(clk'event and clk='1')then wrsigbuf<=wrsig;

wrsigrise<=(not wrsigbuf) and wrsig; end if; end process; process(clk) begin

if(clk'event and clk='1')then

if(wrsigrise='1' and (not idlereg='1'))then send<='1';

elsif(cnt=\ send<='0'; end if; end if; end process; process(clk) begin

if(clk'event and clk='1')then if(send='1')then case cnt is

when \ tx<='0';

idlereg<='1'; cnt<=cnt+'1'; when \ tx<=datain(0); idlereg<='1'; cnt<=cnt+'1';

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异步串行接口电路及通信系统设计

when \ tx<=datain(1); idlereg<='1'; cnt<=cnt+'1'; when \ tx<=datain(2); idlereg<='1'; cnt<=cnt+'1'; when \ tx<=datain(3); idlereg<='1'; cnt<=cnt+'1'; when \ tx<=datain(4); idlereg<='1'; cnt<=cnt+'1'; when \ tx<=datain(5); idlereg<='1'; cnt<=cnt+'1'; when \ tx<=datain(6); idlereg<='1'; cnt<=cnt+'1'; when \ tx<=datain(7); idlereg<='1'; cnt<=cnt+'1'; when \ tx<='1';

idlereg<='1'; cnt<=cnt+'1'; when \ tx<='1';

idlereg<='0'; cnt<=cnt+'1'; when others=> cnt<=cnt+'1'; end case; else

tx<='1'; cnt<='0';

idlereg<='0'; end if;

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异步串行接口电路及通信系统设计

end if; end process; end one;

显示模块 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dyz_disp is port

(clk:in std_logic;

d_out:in std_logic_vector(7 downto 0); en:out std_logic_vector(1 downto 0); led:out std_logic_vector(7 downto 0)); end;

architecture bav of dyz_disp is signal counter:integer range 0 to 7; begin

process(clk)

variable num:std_logic_vector(3 downto 0 ); begin

if rising_edge(clk)then if counter>=7 then counter<=0; else

counter<=counter+1; end if;

case counter is when 0=> en<=\

num:=d_out(7 downto 4); when 1=> en<=\

num:=d_out(3 downto 0); when others=> en<=\num:=\end case; case num is

when \ when \ when \ when \

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异步串行接口电路及通信系统设计

when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \when others=>led<=\end case; end if;

end process; end ;

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