异步串行接口电路及通信系统设计
八、附录
附录Ⅰ：任务分工
资料查找 程序编辑及调试 答辩PPT制作 设计报告撰写
邹燕、孙显珑、姚超、颜利娟 邹燕、姚超、孙显珑、王静 姚超 孙显珑、邹燕、姚超、颜利娟 附录Ⅱ：程序
325分频： library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
entity clkdiv325 is port(
clk:in std_logic; clkout: out std_logic ); end clkdiv325;
architecture one of clkdiv325 is signal cnt:integer:=0; begin
process(clk) begin
if(clk'event and clk='1')then if cnt=324 then cnt<=0; else cnt<=cnt+1;end if; if cnt>=162 then clkout<='1'; else clkout<='0';end if; end if; end process; end one;
20
异步串行接口电路及通信系统设计
地址模块 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity adress1 is
port(clk:in std_logic;
data:in std_logic_vector(7 downto 0); adress:out std_logic_vector(7 downto 0)); end adress1;
architecture bav of adress1 is
signal cnt:std_logic_vector(7 downto 0); signal cnt1:std_logic:='0'; begin
process(clk) begin
if data=\ case cnt1 is
when '1' => if clk'event and clk='1' then
if cnt>=255 then cnt<=\ else cnt<=cnt+1; end if; end if; when others =>null; end case; end if; end process; adress<=cnt; end bav;
rom模块
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf; USE altera_mf.all;
ENTITY rom123 IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
21
异步串行接口电路及通信系统设计
clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );
END rom123;
ARCHITECTURE SYN OF rom123 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL );
PORT ( clock0 : IN STD_LOGIC ; address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );
END COMPONENT; BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => \ clock_enable_output_a => \ init_file => \ intended_device_family => \ lpm_hint => \ lpm_type => \ numwords_a => 256, operation_mode => \ outdata_aclr_a => \
22
异步串行接口电路及通信系统设计
outdata_reg_a => \ widthad_a => 8, width_a => 8, width_byteena_a => 1 )
PORT MAP ( clock0 => clock, address_a => address, q_a => sub_wire0 );
END SYN;
uart接收模块 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
entity dyzrx is
port(clk:in std_logic; rx: in std_logic;
dataout:out std_logic_vector(7 downto 0); rdsig: out std_logic ); end dyzrx;
architecture one of dyzrx is
signal dataoutreg:std_logic_vector(7 downto 0); signal rdsigreg: std_logic;
signal cnt:std_logic_vector(7 downto 0); signal rxbuf:std_logic; signal rxfall:std_logic; signal receive:std_logic; signal idle:std_logic; begin
process(clk) begin
if(clk'event and clk='1')then rxbuf<=rx;
if (rxbuf='1' and rx='0')then rxfall<='1'; else
23
异步串行接口电路及通信系统设计
rxfall<='0'; end if; end if; end process;
process(clk) begin
if(clk'event and clk='1')then if(rxfall='1' and idle='0' ) then receive<='1';
elsif (cnt=\ receive<='0'; end if; end if;
end process;
process(clk) begin
if(clk'event and clk='1')then if(receive='1')then case cnt is
when \ idle<='1'; cnt<=cnt+'1'; rdsig<='0'; when \ idle<='1';
dataout(0)<=rx; cnt<=cnt+'1'; rdsig<='0'; when \ idle<='1';
dataout(1)<=rx; cnt<=cnt+'1'; rdsig<='0'; when \ idle<='1';
dataout(2)<=rx; cnt<=cnt+'1'; rdsig<='0'; when \ idle<='1';
dataout(3)<=rx; cnt<=cnt+'1';
24
百度搜索“77cn”或“免费范文网”即可找到本站免费阅读全部范文。收藏本站方便下次阅读，免费范文网，提供经典小说综合文库异步串行接口电路及通信系统设计设计报告(6)在线全文阅读。
相关推荐：