基于单片机的无功补偿控制器(7)

安徽工程大学毕业设计

参考文献

[1] 王兆安,刘进军,杨君,王跃.谐波抑制和无功功率补偿[M].北京：机械工业出版社,2005 [2] 王瑞兰,马守忠.单片机控制的PWM斩波式交流稳压电源的设计[J].商场现代化，2006，14：8-9

[3] 毛盾,徐清山,权永军.基于可变电压源的混合式电网无功功率连续补偿新方法[J].吉林电力,2003，04：32-34

[4] 孙树勤.无功补偿的矢量控制[M].北京：中国电力出版社，1998

[5] 许海斌,许敏,周谦之.基于开关线性复合功率变换技术的新型无功补偿装置[J].电气传动自动化,2004，26 (1):39-42

[6] 刘丹,黄玉水，周其明.一种基于TL494的PWM控制技术[J].通信电源术, 2007，24（06）：39-41

[7] 罗安.电网谐波治理和无功功率补偿技术及装备[M].北京：中国电力出版社，2006 [8] 罗国颖,鄢峰,张迁,卢超.数控开关电压源的设计与制作[J].电子元器件应用,2010,12（04）：66-72

[9] 姜宁,王春宁,董其国.无功电压与优化技术问答[M].北京：中国电力出版社，2006 [10] 姜齐荣等著.电力系统并联补偿—结构、原理、控制与应用[M].北京：机械工业出版社，2004

[11] 凌志斌,邓超平,郑益慧. 新型连续无功调节控制器的研制[J].电气技工杂志,2003, 08：48-51

[12] 顾学群,刘建峰.单片机无功动态补偿控制器[J].仪表技术,2004，04：32-34 [13] 傅知兰.电力系统电气设备选择与实用计算[M].北京：中国电力出版社，2004

[15] Jayabarathi. R.a and Devarajan. N.b. ANN Based DSPIC Controller for Reactive Power Compensation[J]. American Journal of Applied Sciences 4 (7): 508-515, 2007

[14] Urs Bpegli. Remo Ulmi.Realization of a New Inverter Circuit for Divect Photovoltaic Energy Feedback into the Public Grid[J].IEEE transaction on Industry Applicantions.1986. IA-22(2):255-258

[16] Tripathi. K, Martinez .C.A, Nirenberg. S.,1985. A reactive switching simulation in security analysis at Florida Power and Light System control center, IEEE transactions on Power apparatus and systems: 104:3482-3485

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附录A 硬件电路图

刘德杰：基于单片机的无功补偿控制器硬件电路设计

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安徽工程大学毕业设计

附录B 外文文献及其译文

英文原文：

AT89C51 Data Sheet

Features：

? Compatible with MCS-51? Products

? 4K Bytes of In-System Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles ? Fully Static Operation: 0 Hz to 24 MHz ? Three-level Program Memory Lock ? 128 x 8-bit Internal RAM ? 32 Programmable I/O Lines ? Two 16-bit Timer/Counters ? Six Interrupt Sources

? Programmable Serial Channel

? Low-power Idle and Power-down Modes Description：

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.

Block Diagram：

The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture,

a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two

Software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The

Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

Pin Description：

VCC：Supply voltage. GND：Ground.

Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed low order address/data

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刘德杰：基于单片机的无功补偿控制器硬件电路设计

bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.

Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51 as listed: Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Functions RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (timer 0 external input) T1 (timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) Port 3 also receives some control signals for Flash programming and verification. RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

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安徽工程大学毕业设计

PSEN：Program Store Enable is the read strobe to external program memory.

When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.

XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2：Output from the inverting oscillator amplifier. Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.

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