EDA课程设计拔河游戏机(9)

eda课程设计,游戏机!vhdl语言,Quartus II 7.0

end if; end process;

end devode_body;

e. 音乐模块 library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity music is

port(music_begin:in std_logic; clk_4:in std_logic; clk:in std_logic;

music_out:out std_logic ); 图8 音乐模块 end music;

architecture music_body of music is constant m1:integer:=955; constant m2:integer:=851; constant m3:integer:=758; constant m4:integer:=716; constant m5:integer:=639; constant m6:integer:=569; constant m7:integer:=506; constant m0:integer:=0;

signal counter:integer range 0 to 192; signal count:integer range 0 to 1000; signal sub:integer range 0 to 1000; signal carrier:std_logic;

signal pat,pat1,pat2:std_logic;

begin

process(clk) begin

if(clk'event and clk='1')then if(carrier='1') then sub<=count; else

sub<=sub-1;

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