EDA课程设计拔河游戏机(5)

eda课程设计,游戏机!vhdl语言,Quartus II 7.0

end process;

clk_100<=clk1; clk_4<=clk2; clk_1<=clk3; end division_body; b. 防抖模块 library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity fangdou_player1 is

port( clk_100:in std_logic; player1_b:in std_logic; player1:out std_logic );

图4 防抖1

end fangdou_player1;

architecture fangdou_player1_body of fangdou_player1 is signal mp1,mp2:std_logic; begin

process(clk_100) begin

if(clk_100'event and clk_100='0') then mp2<=mp1;

mp1<=player1_b; end if; end process;

player1<=clk_100 and mp1 and (not mp2); end fangdou_player1_body;

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity fangdou_player2 is

port( clk_100:in std_logic; player2_b:in std_logic; player2:out std_logic );

end fangdou_player2;

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