EDA课程设计拔河游戏机(4)

eda课程设计,游戏机!vhdl语言,Quartus II 7.0

architecture division_body of division is signal count1:integer range 0 to 4999; --signal count1:integer range 0 to 1; signal count2:integer range 0 to 124999; signal count3:integer range 0 to 49; --signal count3:integer range 0 to 1;

signal clk1,clk2,clk3:std_logic; begin

--得到100HZ的频率 process(clk) begin

if(clk'event and clk='1')then if(count1=4999)then count1<=0;

clk1<=not clk1; else count1<=count1+1; end if; end if; end process;

--得到4HZ的频率 process(clk) begin

if(clk'event and clk='1') then if(count2=124999) then count2<=0;

clk2<=not clk2; else count2<=count2+1; end if; end if; end process;

--得到1HZ的频率 process(clk1) begin

if(clk1'event and clk1='1') then if(count3=49) then count3<=0;

clk3<=not clk3; else count3<=count3+1;

end if;

图3 分频器

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