Xilinx FPGA PCIE Linux驱动程序(3)

//---START: Initialize Hardware

// Check the memory region to see if it is in use

if (check_mem_region(gBaseHdwr, XBMD_REGISTER_SIZE) < 0) {

printk(KERN_WARNING\, gDrvrName); return (CRIT_ERR); }

// Try to gain exclusive control of memory for demo hardware.

request_mem_region(gBaseHdwr, XBMD_REGISTER_SIZE, \); // Update flags

gStatFlags = gStatFlags | HAVE_REGION;

printk(KERN_INFO\,gDrvrName);

// Request IRQ from OS.

// In past architectures, the SHARED and SAMPLE_RANDOM flags were called: SA_SHIRQ and SA_SAMPLE_RANDOM

// respectively. In older Fedora core installations, the request arguments may need to be reverted back.

// SA_SHIRQ | SA_SAMPLE_RANDOM

printk(KERN_INFO\, gDrvrName);

if (request_irq(gIrq, &XPCIe_IRQHandler, IRQF_SHARED | IRQF_SAMPLE_RANDOM, gDrvrName, gDev) < 0) {

printk(KERN_WARNING\,gDrvrName); return (CRIT_ERR); }

// Update flags stating IRQ was successfully obtained gStatFlags = gStatFlags | HAVE_IRQ;

// Bus Master Enable

if (pci_enable_device(gDev) < 0) {

printk(KERN_WARNING\, gDrvrName); return (CRIT_ERR); }

//--- END: Initialize Hardware

//--- START: Allocate Buffers

// Allocate the read buffer with size BUF_SIZE and return the starting address gReadBuffer = pci_alloc_consistent(gDev, BUF_SIZE, &gReadHWAddr); if (NULL == gReadBuffer) {

printk(KERN_CRIT\,gDrvrName); return (CRIT_ERR); }

// Print Read buffer size and address to kernel log

printk(KERN_INFO\, gDrvrName, (unsignedint)gReadBuffer, (unsignedint)gReadHWAddr);

// Allocate the write buffer with size BUF_SIZE and return the starting address

gWriteBuffer = pci_alloc_consistent(gDev, BUF_SIZE, &gWriteHWAddr); if (NULL == gWriteBuffer) {

printk(KERN_CRIT\,gDrvrName); return (CRIT_ERR); }

// Print Write buffer size and address to kernel log

printk(KERN_INFO\Write Buffer Allocation: %X->%X\\n\, gDrvrName, (unsignedint)gWriteBuffer, (unsignedint)gWriteHWAddr);

//--- END: Allocate Buffers

//--- START: Register Driver

// Register with the kernel as a character device.

if (register_chrdev(gDrvrMajor, gDrvrName, &XPCIe_Intf) < 0) {

printk(KERN_WARNING\, gDrvrName); return (CRIT_ERR); }

printk(KERN_INFO\, gDrvrName); gStatFlags = gStatFlags | HAVE_KREG;

//--- END: Register Driver // The driver is now successfully loaded. All HW is initialized, IRQ's assigned, and buffers allocated printk(\, gDrvrName);

// Initializing card registers XPCIe_InitCard();

return 0; }

//--- XPCIe_InitiatorReset(): Resets the XBMD reference design //--- Arguments: None //--- Return Value: None

//--- Detailed Description: Writes a 1 to the DCSR register which resets the XBMD design void XPCIe_InitiatorReset() {

XPCIe_WriteReg(0, 1); // Write: DCSR (offset 0) with value of 1 (Reset Device) XPCIe_WriteReg(0, 0); // Write: DCSR (offset 0) with value of 0 (Make Active) }

//--- XPCIe_InitCard(): Initializes XBMD descriptor registers to default values //--- Arguments: None //--- Return Value: None

//--- Detailed Description: 1) Resets device

//--- 2) Writes specific values into the XBMD registers inside the EP void XPCIe_InitCard() {

XPCIe_WriteReg(0, 1); // Write: DCSR (offset 0) with value of 1 (Reset Device)

XPCIe_WriteReg(0, 0); // Write: DCSR (offset 0) with value of 0 (Make Active)

XPCIe_WriteReg(2, gWriteHWAddr); // Write: Write DMA TLP Address register with starting address

XPCIe_WriteReg(3, 0x20); // Write: Write DMA TLP Size register with default value (32dwords)

XPCIe_WriteReg(4, 0x2000); // Write: Write DMA TLP Count register with default value (2000)

XPCIe_WriteReg(5, 0x00000000); // Write: Write DMA TLP Pattern register with default value (0x0)

XPCIe_WriteReg(6, 0xfeedbeef); // Write: Read DMA Expected Data Pattern with default value (feedbeef)

XPCIe_WriteReg(7, gReadHWAddr); // Write: Read DMA TLP Address register with starting address.

XPCIe_WriteReg(8, 0x20); // Write: Read DMA TLP Size register with default value (32dwords)

XPCIe_WriteReg(9, 0x2000); // Write: Read DMA TLP Count register with default value (2000) }

//--- XPCIe_exit(): Performs any cleanup required before releasing the device //--- Arguments: None //--- Return Value: None

//--- Detailed Description: Performs all cleanup functions required before releasing device staticvoid XPCIe_exit(void) {

// Check if we have a memory region and free it if (gStatFlags & HAVE_REGION) {

(void) release_mem_region(gBaseHdwr, XBMD_REGISTER_SIZE); }

// Check if we have an IRQ and free it if (gStatFlags & HAVE_IRQ) {

(void) free_irq(gIrq, gDev); }

// Free Write and Read buffers allocated to use if (NULL != gReadBuffer) {

(void) kfree(gReadBuffer); }

if (NULL != gWriteBuffer) {

(void) kfree(gWriteBuffer); }

// Free memory allocated to our Endpoint

pci_free_consistent(gDev, BUF_SIZE, gReadBuffer, gReadHWAddr); pci_free_consistent(gDev, BUF_SIZE, gWriteBuffer, gWriteHWAddr);

gReadBuffer = NULL; gWriteBuffer = NULL;

// Free up memory pointed to by virtual address if (gBaseVirt != NULL) {

iounmap(gBaseVirt); }

gBaseVirt = NULL;

// Unregister Device Driver if (gStatFlags & HAVE_KREG) {

unregister_chrdev(gDrvrMajor, gDrvrName); }

gStatFlags = 0;

// Update Kernel log stating driver is unloaded

printk(KERN_ALERT\, gDrvrName); }

// Driver Entry Point module_init(XPCIe_init);

// Driver Exit Point module_exit(XPCIe_exit);

void XPCIe_IRQHandler(int irq, void *dev_id, struct pt_regs *regs) {

u32 i, regx;

printk(KERN_WARNING\,gDrvrName);

for (i = 0; i < 32; i++) {

regx = XPCIe_ReadReg(i);

printk(KERN_WARNING\, gDrvrName, i, regx); }

printk(KERN_WARNING\, gDrvrName); }

u32 XPCIe_ReadReg (u32 dw_offset) {

u32 ret = 0;

//u32 reg_addr = (u32)(gBaseVirt + (4 * dw_offset)); //ret = readl(reg_addr);

ret = readl(gBaseVirt + (4 * dw_offset));

return ret; }

void XPCIe_WriteReg (u32 dw_offset, u32 val) {

//u32 reg_addr = (u32)(gBaseVirt + (4 * dw_offset)); writel(val, (gBaseVirt + (4 * dw_offset))); }

ssize_t* XPCIe_ReadMem(char *buf, size_t count) {

int ret = 0;

dma_addr_t dma_addr;

//make sure passed in buffer is large enough if ( count < BUF_SIZE ) {

printk(\, gDrvrName); ret = -1; return ret; //goto exit; }

down(&gSem[SEM_DMA]);

// pci_map_single return the physical address corresponding to // the virtual address passed to it as the 2nd parameter // 获取DMA总线地址,底层调用的是pci_map_single

dma_addr = pci_map_single(gDev, gReadBuffer, BUF_SIZE, PCI_DMA_FROMDEVICE); if ( 0 == dma_addr ) {

printk(\,gDrvrName); ret = -1;

up(&gSem[SEM_DMA]); return ret;

//goto exit; // return 之前要释放互斥量，不能直接return }

// Now pass the physical address to the device hardware. This is now // the destination physical address for the DMA and hence the to be // put on Memory Transactions

// Do DMA transfer here....

// 直接调用read write 函数进行传输? // 宋宝华第页流程图

printk(\, gDrvrName, (unsignedint)gReadBuffer, (unsignedint)dma_addr);

// Unmap the DMA buffer so it is safe for normal access again.

pci_unmap_single(gDev, dma_addr, BUF_SIZE, PCI_DMA_FROMDEVICE);

up(&gSem[SEM_DMA]);

// Now it is safe to copy the data to user space. if ( copy_to_user(buf, gReadBuffer, BUF_SIZE) ) {

ret = -1;

printk(\,gDrvrName);

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