AD9226-LQFP-EB中文资料(7)

The same midsupply potential may be obtained from theCMLEVEL pin of the AD9226 in the LQFP package.

Referring to Figure 7, a series resistor, RS, is inserted between theAD9226 and the secondary of the transformer. The value of33 ohm was selected to specifically optimize both the THD andSNR performance of the ADC. RS and the internal capacitancehelp provide a low-pass filter to block high-frequency noise.Transformers with other turns ratios may also be selected tooptimize the performance of a given application. For example, agiven input signal source or amplifier may realize an improve-ment in distortion performance at reduced output power levelsand signal swings. By selecting a transformer with a higherimpedance ratio (e.g., Minicircuits T16-6T with a 1:16 imped-ance ratio), the signal level is effectively “stepped up” thusfurther reducing the driving requirements of signal source.

Figure 8.Simple Clamping Circuit

AC-COUPLING AND INTERFACE ISSUES

For applications where ac-coupling is appropriate, the op ampoutput can be easily level-shifted by means of a couplingcapacitor. This has the advantage of allowing the op amp’s com-mon-mode level to be symmetrically biased to its midsupplylevel (i.e., (AVDD/2). Op amps that operate symmetrically withrespect to their power supplies typically provide the best acperformance as well as greatest input/output span. Various high-speed performance amplifiers that are restricted to +5 V/–5 Voperation and/or specified for 5 V single-supply operation can beeasily configured for the 2 V or 1 V input span of the AD9226.

Simple AC Interface

Figure 7.Transformer-Coupled Input

Figure 9a shows a typical example of an ac-coupled, single-ended configuration of the SSOP package. The bias voltageshifts the bipolar, ground-referenced input signal to approxi-mately AVDD/2. The capacitors, C1 and C2, are 0.1 µF ceramicand 10 µF tantalum capacitors in parallel to achieve a lowcutoff frequency while maintaining a low impedance over awide frequency range. The combination of the capacitor and theresistor form a high-pass network with a high-pass –3 dB fre-quency determined by the equation,

f–3 dB = 1/(2 × π × R × (C1 + C2))

–16–

REV. 0

AD9226

The low-impedance VREF output can be used to provide dcbias levels to the fixed VINB pin and the signal on VINA. Fig-ure 9b shows the VREF configured for 2.0 V, thus the inputrange of the ADC is 1.0 V to 3.0 V. Other input ranges couldbe selected by changing VREF.

When the inputs are biased from the reference (Figure 9b),there may be a slight degeneration of dynamic performance. Amidsupply output level is available at the CM LEVEL pin of theLQFP package.

Figure 10 illustrates the relation between common-mode voltageand THD. Note that optimal performance occurs when thereference voltage is set to 2.0 V (input span = 2.0 V).

DC-COUPLING AND INTERFACE ISSUES

Many applications require the analog input signal to be dc-coupledto the AD9226. An operational amplifier can be configured torescale and level-shift the input signal to make it compatiblewith the selected input range of the ADC.

The selected input range of the AD9226 should be consideredwith the headroom requirements of the particular op amp toprevent clipping of the signal. Many of the new high-performanceop amps are specified for only ±5 V operation and have limitedinput/output swing capabilities. Also, since the output of a dualsupply amplifier can swing below absolute minimum (–0.3 V),clamping its output should be considered in some applications(see Figure 8). When single-ended, dc-coupling is needed, theuse of the AD8138 in a differential configuration (Figure 9a) ishighly recommended.

Simple Op Amp Buffer

Figure 9a.AC-Coupled Input Configuration

In the simplest case, the input signal to the AD9226 will alreadybe biased at levels in accordance with the selected input range. Itis necessary to provide an adequately low source impedance forthe VINA and VINB analog pins of the ADC.

REFERENCE OPERATION

The AD9226 contains an on-board bandgap reference thatprovides a pin-strappable option to generate either a 1 V or2V output. With the addition of two external resistors, the usercan generate reference voltages between 1 V and 2 V. SeeFigures 5a-5f for a summary of the pin-strapping options for theAD9226 reference configurations. Another alternative is to usean external reference for designs requiring enhanced accuracyand/or drift performance described later in this section.Figure 11a shows a simplified model of the internal voltage refer-ence of the AD9226. A reference amplifier buffers a 1 V fixedreference. The output from the reference amplifier, A1, appearson the VREF pin. The voltage on the VREF pin determinesthe full-scale input span of the ADC. This input span equals,

Full-Scale Input Span = VREF

The voltage appearing at the VREF pin, and the state of theinternal reference amplifier, A1, are determined by the voltageappearing at the SENSE pin. The logic circuitry contains com-parators that monitor the voltage at the SENSE pin. If theSENSE pin is tied to AVSS, the switch is connected to theinternal resistor network thus providing a VREF of 2.0 V. If theSENSE pin is tied to the VREF pin via a short or resistor, theswitch will connect to the SENSE pin. This connection will pro-vide a VREF of 1.0 V. An external resistor network will providean alternative VREF between 1.0 V and 2.0 V (see Figure 12).Another comparator controls internal circuitry that will disablethe reference amplifier if the SENSE pin is tied to AVDD.Disabling the reference amplifier allows the VREF pin to bedriven by an external voltage reference.

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