AD9226-LQFP-EB中文资料(5)

TPC 22.Dual-Tone SNR and SFDR with fIN–1 = 44.2 MHzand fIN–2 = 45.6 MHz

9085z

H/S

F80

SFBd Bd –– R75

RDFSOOL/RF NES70

SINO65

60AIN – dBFS

TPC 23.Dual-Tone SNR and SFDR with fIN–1 = 69.2 MHzand fIN–2 = 70.6 MHz

z

H/S

SFFBBdd –– RRDFSOOL/RF NESSINOAIN – dBFS

TPC 24.Dual-Tone SNR and SFDR with fIN–1 = 139.2 MHzand fIN–2 = 140.7 MHz

–12–REV. 0

––––S

–FBd–––––––FREQUENCY – MHz

TPC 25.Single-Tone 8K FFT at IF = 190 MHz–WCDMA(fIN = 190.82 MHz, fSAMPLE = 61.44 MSPS)––––S

–FBd–––––––0

12

16

24

28

FREQUENCY –

MHz

TPC 26.Dual-Tone 8K FFT with fIN–1 = 239.1 MHz andfIN–2

= 240.7 MHz–35

–45

–55

c

Bd – R–65RMC–75

–85–FREQUENCY – MHz

TPC 27.CMRR vs. Frequency (AIN = –0 dBFS andCML = 2.5 V)

REV. 0AD9226

zH/S

SFFBBdd –– RRDFSOOL/RF NESSINOAIN – dBFS

TPC 28.Single-Tone SNR and SFDR vs. AIN at IF = 190MHz–WCDMA (fIN–1 = 190.8 MHz, fSAMPLE = 61.44MSPS)

z

H/S

SFFBBdd –– RRDOFSOL/RF NESSIONAIN – dBFS

TPC 29.Dual-Tone SNR and SFDR with fIN–1 = 239.1 MHzand fIN–2 = 240.7 MHz

–13–

AD9226

THEORY OF OPERATION

The AD9226 is a high-performance, single-supply 12-bit ADC.The analog input of the AD9226 is very flexible allowing for bothsingle-ended or differential inputs of varying amplitudes that canbe ac- or dc-coupled.

It utilizes a nine-stage pipeline architecture with a wideband,sample-and-hold amplifier (SHA) implemented on a cost-effective CMOS process. A patented structure is used in theSHA to greatly improve high frequency SFDR/distortion. Thisalso improves performance in IF undersampling applications.Each stage of the pipeline, excluding the last stage, consists of alow resolution flash ADC connected to a switched capacitorDAC and interstage residue amplifier (MDAC). The residueamplifier amplifies the difference between the reconstructed DACoutput and the flash input for the next stage in the pipeline. Onebit of redundancy is used in each of the stages to facilitate digitalcorrection of flash errors. The last stage simply consists of aflash ADC.

Factory calibration ensures high linearity and low distortion.

ANALOG INPUT OPERATION

and/or shunt capacitor can help limit the wideband noise at theADC’s input by forming a low-pass filter. The source imped-ance driving VINA and VINB should be matched. Failure toprovide matching will result in degradation of the AD9226’sSNR, THD, and SFDR.

Figure 3.Equivalent Input Circuit

Figure 3 shows the equivalent analog input of the AD9226 whichconsists of a 750 MHz differential SHA. The differential inputstructure of the SHA is highly flexible, allowing the device to beeasily configured for either a differential or single-ended input.The analog inputs, VINA and VINB, are interchangeable withthe exception that reversing the inputs to the VINA and VINBpins results in a data inversion (complementing the output word).The optimum noise and dc linearity performance for either

differential or single-ended inputs is achieved with the largest inputsignal voltage span (i.e., 2 V input span) and matched inputimpedance for VINA and VINB. Only a slight degradation indc linearity performance exists between the 2 V and 1 V inputspans.

High frequency inputs may find the 1 V span better suited toachieve superior SFDR performance. (See Typical Perfor-mance Characteristics.)

The ADC samples the analog input on the rising edge of the clockinput. During the clock low time (between the falling edge andrising edge of the clock), the input SHA is in the sample mode;during the clock high time it is in hold. System disturbances justprior to the rising edge of the clock and/or excessive clock jitteron the rising edge may cause the input SHA to acquire the wrongvalue and should be minimized.

When the ADC is driven by an op amp and a capacitive load isswitched onto the output of the op amp, the output will momen-tarily drop due to its effective output impedance. As the outputrecovers, ringing may occur. To remedy the situation, a seriesresistor can be inserted between the op amp and the SHAinput as shown in Figure 4. A shunt capacitance also acts likea charge reservoir, sinking or sourcing the additional chargerequired by the hold capacitor, CH, further reducing currenttransients seen at the op amp’s output.

The optimum size of this resistor is dependent on several factors,including the ADC sampling rate, the selected op amp, and theparticular application. In most applications, a 30 to 100 resistor is sufficient.

For noise-sensitive applications, the very high bandwidth of theAD9226 may be detrimental and the addition of a series resistor

Figure 4.Series Resistor Isolates Switched-CapacitorSHA Input from Op Amp; Matching Resistors ImproveSNR Performance

OVERVIEW OF INPUT AND REFERENCECONNECTIONS

The overall input span of the AD9226 is equal to the potentialat the VREF pin. The VREF potential may be obtained fromthe internal AD9226 reference or an external source (seeReference Operation section).

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