T2<=(NOT X(1))AND X(0); T3<=X(1)AND (NOT X(0)); T4<=X(1)AND X(0); END IF; END PROCESS; END A;
13.11: 微程序控制器单元
微程序控制器单元
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微程序控制器的内部结构
13.11.1: 地址转移逻辑电路
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADDR IS PORT(
I7,I6,I5,I4:IN STD_LOGIC; FZ,FC,T4,P1,P2:IN STD_LOGIC;
SE6,SE5,SE4,SE3,SE2,SE1:OUT STD_LOGIC );
END ADDR;--地址转移逻辑电路 ARCHITECTURE A OF ADDR IS BEGIN SE6<='1';
SE5<=NOT ((NOT FC OR FZ ) AND P2 AND T4); SE4<=NOT(I7 AND P1 AND T4); SE3<=NOT(I6 AND P1 AND T4); SE2<=NOT(I5 AND P1 AND T4); SE1<=NOT(I4 AND P1 AND T4); END A;
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13.11.2: 微地址寄存器
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微地址寄存器内部结构
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MMM IS PORT(
SE:IN STD_LOGIC; T2:IN STD_LOGIC; D:IN STD_LOGIC; CLR:IN STD_LOGIC; UA:OUT STD_LOGIC );
END MMM;--带有异步清零和异步置一功能的触发器，由多个mmm组成微地址寄存器aa
ARCHITECTURE A OF MMM IS BEGIN
PROCESS(CLR,SE,T2) BEGIN
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