外文翻译(8)

12 Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 11. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 12.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by -two flip-flop, but minimum and maximum voltage high and low time specific ations must be observ ed.

Figure 11. Oscillator Connections Figure 12. External Clock Drive Configuration

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Note: C1, C2 = 30 pF ??10 pF for Crystals

= 40 pF ??10 pF for Ceramic Resonators

12.1 Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchange d during t his mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware reset , the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but acc ess to the port pins is not inhibited. To eliminate the poss ibility of an unexpected write to a port pin when idle mode is terminat ed by areset, the instruction following the one that invokes idle mode should not write to a port pin or to ex ternal memory. 12.2 Power-down Mode

In the Power-down mode, the oscillator is stopped, and the ins truction that inv okes Power-down is the last instruction executed.The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt.Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

Table 6. Status of External Pins During Idle and Power-down Modes

Mode Idle Idle Program Memory Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 PORT1 PORT2 Data Float Data Float Data Data Data Data Data Address Data Data PORT3 Data Data Data Data Power-down Internal Power-down External

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13 Program Memory Lock Bits

The AT89S52 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table.

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly.

14 Programming the Flash – Parallel Mode

The AT89S52 is shipped with the on-chip Flash memory array ready to be programmed.The programming interface needs a high-voltage(12-volt) program enable signal and is compatible with conventional third-party Flash or EPROM programmers. The AT89S52 code memory array is programmed byte-by-byte. 14.1 Programming Algor ithm

Before programming the AT89S52, the address, data, and control signals should be set up according to the Flash programming mode table and Figures 13 and 14. To program the AT89S52, take the following steps:

1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V.

5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 50 μs. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the objec t file is reached. 14.2 Data Polling

The AT89S52 features Data Polling to indi-cate the end of a byte write cycle.

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