研究生文献检索作业(3)

【作者】Yanjun Zhang，Hu He，Zheng Shen，Yihe Sun，Tsinghua 【刊名】Science & Technology

【摘要】The rapid development of multimedia techniques has increased the demands on multimedia processors. This paper presents a new design method to quickly design high performance processors for new multimedia applications. In this approach, a configurable processor based on the very long instruction-set word architecture is used as the basic core for designers to easily configure new processor cores for multimedia algorithm. Specific instructions designed for multimedia applications efficiently improve the performance of the target processor. Functions not implemented in the digital signal processor (DSP) core can be easily integrated into the target processor as user-defined hardware to increase the performance. Several examples are given based on the architecture. The results show that the processor performance is enhanced approximately 4 times on the H.263 codec and that the processor outperforms both DSPs and single instruction multiple data (SIMD) multimedia extension architectures by up to 8 times when computing the 2-D-IDCT.

13) 【篇名】Mapping of nomadic multimedia applications on the ADRES

reconfigurable array processor

【作者】Andreas Kanstein，Bingfeng Mei，Bjorn De Sutter 【刊名】Microprocessors and Microsystems 【摘要】This paper introduces the mapping of MPEG video decoders on ADRES, IMEC’s new coarse-grain reconfigurable and fully C-programmable array processor that targets nomadic devices. ADRES is a flexible template that allows the instantiation of many different processor versions. An XML-based architecture description language allows a designer to easily generate different processor instances with full compiler support by specifying different values for the communication topology, the number and size of local register files and functional units and supported instruction set. ADRES supports a VLIW-like programming model with a pure VLIW mode for legacy code, and a (coarse-grain reconfigurable) array mode with very high parallelism for the processing of compute intensive loops. We demonstrate the mapping of two video decoders MPEG-2 and AVC, and discuss the performance trade-offs for two critical kernels: IDCT and integer transform. As a result, an ADRES based system can perform AVC decoding in CIF resolution with less then 50 MHz on a 4 × 4 array processor.

14) 【篇名】Testing process performance based on the yield: an application to

the liquid-crystal display module 【作者】Jann-Pygn Chen，W. L. Pearn 【刊名】Microelectronics Reliability

【摘要】Process capability indices have been introduced to provide numerical measures on whether a manufacturing process is capable of reproducing items meeting the specifications predetermined by the product designers or the consumers. Process yield is one of the most common criteria used in the manufacturing industry for measuring process performance. The formula Spk has been proposed to calculate the process yield for normal processes. The formula Spk provides an exact measure on the process yield. Unfortunately, the statistical properties of the estimated are

mathematically intractable. In this paper, we apply the bootstrap simulation method to construct the lower confidence bound of Spk. We then present a real-world application to the liquid-crystal display module process, to illustrate how we may apply the formula Spk to actual data collected from the factories.

15) 【篇名】CBP and ART image reconstruction algorithms on media and DSP

processors

【作者】K. Rajan，L. M. Patnaik

【刊名】Microprocessors and Microsystems

【摘要】Computed Tomography (CT) image reconstruction algorithms such as convolution back-projection (CBP) and algebraic reconstruction technique (ART) are highly compute-intensive for today's single processor systems. In this work, we investigate the suitability of TM-1000 media processor and Analog Device's ADSP 21160 as a compute engine for the execution of image reconstruction algorithms.

Philips Trimedia TM-1000, a very large instruction word (VLIW) processor, is a high performance media processor optimized for real-time processing of audio, video, graphifcs, and communication data streams. TM-1000 has a high performance digital signal processor (DSP) core, supported by multiple functional units. The DSP core and the functional blocks operate in parallel, driven by a mix of RISC, multimedia, SIMD-type DSP and floating point instructions. A typical DSP such as Analog Device's ADSP 21160 is based on super harvard architecture (SHARC) and is an optimized processor for digital signal processing applications. It has two sets of computation units. Each computation unit comprises of three functional blocks namely, arithmetic and logic unit (ALU), multiplier and shifter unit. ADSP 21160 supports single instruction multiple data (SIMD) computation model to handle dual computation units. Both sets of computation units operate concurrently.

We compare the performance of TM-1000 media processor and ADSP 21160 DSP processor to execute the image reconstruction algorithms by comparing the execution time of CBP and ART algorithms on them. The image reconstruction algorithms normally break down to a repetitive multiply-accumulate operation (MAC). All DSP processors support single-cycle MAC and zero-overhead loop instructions. The media processors normally do not support single-cycle MAC instruction and zero-overhead loop functionality. However, media processors are equipped with multiple functional units that perform multiple operations in a single instruction time. A DSP processor is expected to execute image reconstruction algorithms much faster than a multimedia processor. However, the experimental results show that the execution time on DSP and media processor are more or less same when 16-bit representation is used for data. When floating point data is used for implementation, DSP processor has an edge. ADSP 21160 gives same execution time for both floating point and 16-bit fixed point data. But, the execution time almost doubles when data is in floating point format on the media processor, compared to a 16-bit implementation. This can be attributed to the fact that TM-1000 processes two sets of operands in a single instruction time when data is in 16-bit format. The executable code for ADSP 21160 was generated from an optimized assembly language program whereas the executable code for TM-1000 was generated from an optimized ‘C’ with a few

custom operations.

16) 【篇名】Control electronic platform based on floating-point DSP and FPGA

for a NPC multilevel back-to-back converter 【作者】Francisco J. Rodríguez; Santiago Cobreces; Emilio J. Bueno; Felipe Espinosa

【刊名】Electric Power Systems Research

【摘要】Modern energy concepts as Distributed Power Generation are changing the appearance of electric distribution and transmission and challenging power electronics researchers, which try to develop new solutions of electronic controllers. The aim is to enable the implementation of new and more complex control algorithms to verify the last standards related to the grid energy quality for new power converters, and, also, for equipments which nowadays are operating. This paper presents the design, implementation and test of a novel real-time controller for a Neutral Point Clamped (NPC) (three-level) multilevel converter based on a floating-point Digital Signal Processor (previous termDSPnext term) and on a Field-Programmable Gate Array (FPGA), by operating in a cooperative way. Although the proposed system can be readily applied to any power electronic application, in this work, it is focused on the next system: a 150 kVA back-to-back three-level NPC Voltage Source Converter (VSC) for wind power applications.

17) 【篇名】An analogue video interface for general-purpose DSP 【作者】I.Y Soon;C.K Yeo;H.C Ng

【刊名】Microprocessors and Microsystems

【摘要】This paper presents a real-time, high speed interface for the capture of live analogue video for previous termDSPnext term based video processing applications. The interface makes use of the link ports, which are standard features of general-purpose digital signal processor (previous termDSPnext term). Hence the interface can be used for the different DSPs with minimum customisation. Current technologies for video processing are either based on application-specific integrated circuit (ASIC) or programmable processors specialised for video or video previous termDSPnext term as well as a hybrid of the above with a host computer. Such technologies come equip with software tools and application programming interfaces (APIs) to support a variety of common video processing tasks. Some of these may have support for analogue video interfaces while others simply cater only to digital video inputs/outputs. Unfortunately, the majority of video sources in daily life are analogue in nature. Video application designers are thus faced with the problem of finding a suitable simple analogue video interface for their applications. Moreover, for those designers who design their own video processing algorithms using general-purpose previous termDSPnext term to circumvent the cost and limitations imposed by these suites of standard solutions, the need for a simple analogue video interface is further underscored. The proposed interface thus serves to provide a simple, flexible, high speed and low-cost analogue interface to resolve the analogue video conversion problem and allow designers to concentrate on their previous termDSPnext term based applications. The interface can support both real-time and non real-time applications.

(2) 硕士论文

1) 【篇名】基于DSP的视频采集及网络传输模块的设计 【作者】韩庭宇

【学校】哈尔滨理工大学

【摘要】DSP的高速数据处理能力使其在语音、图像、编码、数字设备、通信系统、医疗系统、航空航天等方面得到了广泛的应用。尤其是在视频图像压缩编码方面，通过将DSP技术与Internet技术相结合，使图像的远程传输变得越来越容易。采用合理的传输技术和压缩编码，可在网络带宽有限时提高信息的传输效率。DSP系统可以在安全保护、远程医疗等领域获得更加广泛的应用。

针对传统基于PC网络摄像机的稳定性差、效率低以及系统结构复杂等问题，本文提出了基于DM642的网络摄像机的设计方案。通过对流媒体协议的研究，对基于DM642的网络摄像机进行硬件和软件设计，实现了视频采集、视频信号处理、网络实时传输、过程控制等功能的集成。结果表明使用DM642专用视频处理芯片设计的网络摄像机可以显著提高网络摄像机的整体效率和性能，较好地解决了传输速率与图像质量之间的矛盾，同时也利于产品化和升级。

文中详细介绍了网络摄像机各模块的设计，重点阐述了图像采集和网络传输以及嵌入式实时操作系统的程序设计。讨论了流媒体传输算法中的两大关键因素：码率分配和带宽估计，并确定了通过控制TCP/IP传输层协议，在不同的传输任务中使用不同的传输方式以达到流媒体高效传输的目的。通过设计带有网络通信功能的应用程序，实现了视频数据在客户端的呈现。论文最后对系统做了基本的性能测试与总结，并提出了进一步完善和改进的设想与路线。

2) 【篇名】基于电话线的图文声信号传输技术和系统的研制 【作者】厚琳 【学校】中北大学

【摘要】本系统主要针对普通的固定电话交流形方式单一的不足，在原来只传输语音的基础上再加入手写图文信号的输入与传输，是对视频通讯设备的开发。这些新加的功能，可以有效地解除由于方言间不通造成的表述上的误会。还可以满足在电话通讯过程中对图形、路线、设计的探讨。更重要的是，可以极大地降低对使用者的限制。在某些特殊情况下，还具有保密功能；而听力和语言能力有障碍的聋哑人也能自如使用。

本文围绕在普通通讯设备添加手写显示部分，获取图文信号，并传输语音信号的基础上两路信号同时传输的软硬件实现，开展了以下工作：

1 设计了一个基于电话线传输图文声信号的功能结构方案，该方案以数字信号处理器TMS320C6713为核心，具有快速处理数据，且扩展功能强大的优势。

2 应用DSP芯片进行对信号的处理、控制，完成DSP与手写板、液晶显示模块的连接，实现手写输入信号在液晶显示屏上的显示，验证了软硬件设计的正确性。

3 采用电话线作为模拟语音信号和数据传输的共同信道，选择二进制频移键控调制解调方式将数据信号搬移到较高频段，通过频分多路复用的方法实现两路信号同时传输，并以应用程序实现。

4 针对公共电话网的现实情况，提出了基于DSP的系统在入网后可能遇到的问题，并给出了相应的解决方法。编写的程序和设计的电路，对其他类似的应用都可以起到一定的启迪和参考作用。

3) 【篇名】基于嵌入式的图像采集与传输的研究

【作者】刘步中 【学校】江南大学

【摘要】随着信息化技术的发展和数字化产品的普及，以计算机技术、芯片技术和软件技术为核心的嵌入式系统成为当前研究和应用的热点。微电子技术和嵌入式操作系统的不断发展，为数字网络通信中的视频化视频终端创造了有利条件。嵌入式技术与网络、通信和视频技术的相互融合将成为数字视频通信领域的发展趋势。因而基于嵌入式技术实现视频的采集、压缩编码、网络传输、解码播放是移动视频终端应用的坚实基础，有着广阔的发展前景。

本文旨在利用H.264视频压缩编码标准在嵌入式ARMLinux平台上进行实时视频通信系统终端的开发与研究。实验平台选用S3C2440A微处理器的ARM开发扳，将嵌入式Linux技术与H.264视频通信技术相结合，提出了一种基于嵌入式视频服务器的H.264实时视频采集与网络传输系统的方案。此方案对嵌入式视频通信系统的设计开发，具有借鉴意义和实用价值。

论文的主要工作表现在以下几个方面：

1．嵌入式实时视频采集系统的设计，包括USB摄像头驱动程序设计、摄像头驱动程序在Linux系统下的编译移植和实时视频采集应用程序的实现、调试和测试。

2．基于嵌入式实时视频编码方案的设计与优化。结合视频应用的场景特点，选择设计了一款对图像质量损失小、编码速度快的x264编码方案。并结合嵌入式ARM的硬件特点，对x264编码方法进行了优化，主要包括编译级优化、C语言级优化和帧间预测算法优化。最后将优化后的x264编码器成功移植到ARM开发板上。

3．基于RTP的网络实时传输系统和解码播放系统的设计。针对流媒体数据独有的特点，提出一种新的视频传输播放方案：发送端利用RTP协议根据视频压缩编码方式进行分组封装(即打包)，再通过网络实时传输；在接收端，对接收到的视频数据进行分组解析(即拆包)，实现了重建视频帧。最后在PC机Linux环境下实现解码播放。

本设计开发的嵌入式图像采集与传输系统，摄像头采集速度可达13fps，优化后的x264编码器在平均码率为128kbit/s时，编码速度可达到16.81fps左右。虽然传输系统仍存在着大约0.5s左右的延迟，但可以满足大多数嵌入式应用的实时要求。

4) 【篇名】基于手写数字识别算法的DSP实现 【作者】赵凯

【学校】武汉工业学院

【摘要】模式识别是当前国内外研究的一个热点领域。判断一个模式识别算法的优劣可以通过IRIS数据检测和手写数字识别的水平来体现。手写数字识别被认为与汉字识别具有相当的难度，手写数字识别不仅仅用来检验一个识别方法的优劣，对其研究还大大促进了识别方法的研究和模式识别领域的拓广，因此，手写数字识别又是模式识别领域内的一个重要研究课题。高速度、高精度的手写数字识别系统可以代替人工完成数据录入、邮政编码及银行票据的识别等繁重的工作，极大地提高工作速度和效率，具有广阔的应用前景。

在图像分析处理中，FCM聚类算法可以有效地用于图像处理，特别是手写数字识别中。但由于手写数字识别的复杂性，如何设计一种较好的解决方案，以及如何较好地通过软件来实现识别，成为当今研究的集中点。

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