基于CPLD的多功能脉冲分配器系统的设计
end if; end if; end process;
clk_out4 <= clk5 or clk6;
process(cp,rst,mode,clk_outT,clk_outTT,clk_out1, clk_out2,clk_out3,clk_out4) begin
if rst = '1' then
clk_outT <= '0'; else
clk_outT <= clk_outTT; end if;
if mode = \ clk_outTT <= cp; elsif mode = \ clk_outTT <= clk_out1; elsif mode = \ clk_outTT <= clk_out2; elsif mode = \ clk_outTT <= clk_out1; elsif mode = \ clk_outTT <= clk_out3; elsif mode = \ clk_outTT <= clk_out1; elsif mode = \ clk_outTT <= clk_out4; elsif mode = \ clk_outTT <= clk_out1; end if; end process;
clk_out <= clk_outT;
end a;
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盐城工学院本科生毕业设计说明书（2007）
附录3 脉冲分配程序清单
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; entity double3and6 is
port (cp : in std_logic; dir : in std_logic; ex : in std_logic; mode : in std_logic;
outA, outB, outC : out std_logic); end double3and6;
architecture rtl_double3and6 of double3and6 is
type statetype is (state0, state_A, state_AB, state_B, state_BC, state_C, state_AC); signal present_state, next_state :statetype; signal out_A, out_B, out_C : std_logic;
signal trans_value : std_logic_vector (1 downto 0); begin
trans_value <= mode & dir; state_colcked : process (cp, ex) begin
if ex = '1' then
present_state <= state0; elsif cp'event and cp = '1' then present_state <= next_state; end if;
end process state_colcked;
state_comb : process (present_state, next_state, trans_value) begin
case present_state is
when state0 => out_A <= '0'; out_B <= '0'; out_C <= '0'; case trans_value is
when \ when \ when \ when \ when others => next_state <= state0;
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基于CPLD的多功能脉冲分配器系统的设计
end case;
when state_A => out_A <= '1'; out_B <= '0'; out_C <= '0'; case trans_value is
when \ when \ when \ when \ when others => next_state <= state0; end case;
when state_AB => out_A <= '1'; out_B <= '1'; out_C <= '0'; case trans_value is
when \ when \ when \ when \ when others => next_state <= state0; end case;
when state_B => out_A <= '0'; out_B <= '1'; out_C <= '0'; case trans_value is
when \ when \ when \ when \ when others => next_state <= state0; end case;
when state_BC => out_A <= '0'; out_B <= '1'; out_C <= '1'; case trans_value is
when \ when \ when \ when \ when others => next_state <= state0;
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盐城工学院本科生毕业设计说明书（2007）
end case;
when state_C => out_A <= '0'; out_B <= '0'; out_C <= '1'; case trans_value is
when \ when \ when \ when \ when others => next_state <= state0; end case;
when state_AC => out_A <= '1'; out_B <= '0'; out_C <= '1'; case trans_value is
when \ when \ when \ when \ when others => next_state <= state0; end case;
when others => next_state <= state0;
end case;
end process state_comb;
process (cp, out_A, out_B, out_C) begin
if cp' event and cp = '1' then outA <=out_A; outB <=out_B; outC <=out_C; end if; end process; end rtl_double3and6;
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