基于VHDL的uart设计

Uart顶层文件

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity uart is

port(clk,reset:instd_logic;输入时钟及复位按钮 rxd:instd_logic;串行输入端 txd:outstd_logic串行输出端

); end uart;

architecture behavioral of uart is component receive接收器元件例化 port( clkr:instd_logic; reset:instd_logic; rxd:instd_logic; frame_end:outstd_logic; dout:outstd_logic_vector(7 downto 0)); end component;

component Fifo FIFO的元件例化 port( clock : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); rdreq : IN STD_LOGIC ; wrreq : IN STD_LOGIC ; empty : OUT STD_LOGIC ; full : OUT STD_LOGIC ; q:out std_logic_vector(7 downto 0) );

end component;

component baud分频器的元件例化 Port (clkb,resetb:instd_logic; clk_out:outstd_logic); end component;

component transmit发射器的元件例化 PORT( clkt : IN STD_LOGIC; reset : IN STD_LOGIC;

lock : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(7 downto 0); trans : OUT STD_LOGIC; trans_end : OUT STD_LOGIC ); end component;

component flag接受器工作状态原件的例化 port(rxd,clk2 :in std_logic; REN:outstd_logic ); end component;

component counter移位寄存器的元件例化 port(REN,clk2:in std_logic; w,t:outstd_logic ); end component;

signal frame_end,clk2,wrreq,full,empty,REN,w,t,j,k:std_logic;连接线信号的说明 signal dout,data,buf,q,din:std_logic_vector(7 downto 0); signal rdreq,lock,trans,trans_end:std_logic;

begin

wrreq<=frame_end; data<=buf; din<=q; lock<=j; rdreq<=k; txd<=trans;

receive1:receive port map(clk,reset,rxd,frame_end,dout) ;例化元件的引用 baud1:baud port map(clk,reset,clk2);

Fifo1:Fifo port map(clk2,data,rdreq,wrreq,empty,full,q);

transmit1:transmit port map(clk,reset,lock,din,trans,trans_end); flag1:flag port map(rxd,clk2,REN);

counter1:counter port map(REN,clk2,w,t );

process(frame_end,dout)锁存器接收器的frame_end下，将接受器的输出寄存到 beginbuf，收到wrreq信号时，写入fifo if(frame_end='1')then buf<=dout; end if;

end process;

process(REN)输出工作状态选择器

begin REN=0，处于接受状态，令fifo的读操作rdreq及发射器的锁 if REN='1' then存lock为0

j<=w; REN=1，接收counter提供信号w，t分别给rdreq和lock

k<=t; else k<='0'; j<='0'; end if;

end process;

end behavioral;

uart编译结果

Uart功能仿真结果

uart时序仿真结果

Uart接收器

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity receive is

Port (clkr:instd_logic; 时钟输入 reset:instd_logic; 复位端 rxd:instd_logic; 串行输入 frame_end:outstd_logic;工作状态输出 dout:outstd_logic_vector(7 downto 0));并行输出 end receive;

architecture behavioral of receive is begin

pro:process(clkr,reset,rxd)

variable number:std_logic_vector(3 downto 0);

variable count:std_logic_vector(3 downto 0); variable buf:std_logic_vector(7 downto 0); begin

if reset='1' then

number:=\ count:=\frame_end<='1';

elsifrising_edge(clkr) then

if number=\ 判断是否接受到起始位，在clk下连续8个时钟接受为0

if rxd='0' then 0则认为接受到起始位，开始接受数据 if count<\ count:=count+1; else dout<=\

count:=\

number:=number+1; frame_end<='0'; end if;

end if;

elsif number>=\ 接受数据位 if count<\每16个clk时钟接受一位数据位 count:=count+1; else

count:=\

number:=number+1; frame_end<='0';

buf(7 downto 1) := buf(6 downto 0) ; buf(0):=rxd; end if;

elsif number = \接受结束位，到此一帧数据，即十位，接受完毕 if count<\并开始将八位数据输出 count:=count+1; else

count:=\ dout<= buf ; buf:=\

number:=\frame_end<='1';

end if; else

count:=\ number:=\buf:=\frame_end<='1'; end if;

end if; end process; end

behavioral;

百度搜索“77cn”或“免费范文网”即可找到本站免费阅读全部范文。收藏本站方便下次阅读，免费范文网，提供经典小说综合文库基于VHDL的uart设计在线全文阅读。