交通灯设计 verilog(2)

30秒

S0 5秒

S1 5秒

S3 20秒

S2

2.系统设计方案：

根据设计要求和系统所具有功能，并参考相关的文献资料经行方案设计画出如下所示的十字路口交通灯控制器系统框图，及为设计的总体方案，框图如下图所示：

时钟分频模块 CLK 交通灯控制及计时模块 显示模块 LED显示 数码管位码 数码管段码

四、程序设计

6

1.verilog源程序：

module traffic(en,clk,rst,num1,num2,light1,light2,out1,out2,out3,out4,in1,in2);

input en,clk,rst,in1,in2; //en为使能端。in1,in2控制绿灯和红灯亮时间 output [7:0] num1,num2; output [2:0] light1,light2;

output [6:0]out1,out2,out3,out4;//输出四个数码管 reg [6:0]out1,out2,out3,out4; reg tim1,tim2;

reg [1:0]state1,state2; reg [2:0]light1,light2; reg [7:0] num1,num2;

reg [7:0] red1,red2,green1,green2,yellow1,yellow2;

parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;//四个循环状态 reg[25:0]count;reg div;

always @(en ) if(en)

begin //设置计数初值 if (!in1)begin green1<=8'b00110000;red2<=8'b00110000; end//30H,即30秒 else begin green1<=8'b01100000;red2<=8'b01100000;end//60s if (!in2)begin red1<=8'b00100000;green2<=8'b00100000; end//20s else begin red1<=8'b01000000;green2<=8'b01000000; end//40s yellow1<=8'b00000101; yellow2<=8'b00000101;//05s end

always@(posedge clk)//分频 if (count==25000000) begin div<=1;count<=count+1;end else if(count==50000000)begin div<=0;count<=0;end else count<=count+1;

always @(posedge div) begin

if(rst) //复位情况控制 begin

light1<=3'b001; num1<=green1; end else if(en)

begin //使能有效开始控制计数 if(!tim1) //开始控制

begin //主干道交通灯点亮控制 tim1<=1;

case(state1)//状态机

7

s0:begin num1<=green1;light1<=3'b001;state1<=s1;end

s1:begin num1<=yellow1;light1<=3'b010;state1<=s2;end s2:begin num1<=red1;light1<=3'b100;state1<=s3;end s3:begin num1<=yellow1;light1<=3'b010;state1<=s0;end default:light1<=3'b100; endcase end

else

begin //倒数计时 if(num1>0)

if(num1[3:0]==0) begin

num1[3:0]<=4'b1001;

num1[7:4]<=num1[7:4]-1;//十位减1 end

else num1[3:0]<=num1[3:0]-1; //个位减1 if(num1==1) tim1<=0; end end

else begin

light1<=3'b010; num1=2'b00; tim1<=0; end end

always @(posedge div ) //从干道 begin

if(rst) //复位情况控制 begin

light2<=3'b100; num2<=red2; end

else if(en) begin if(!tim2) begin tim2<=1; case(state1)

s0:begin num2<=red2;light2<=3'b100;state2<=s1;end s1:begin num2<=yellow1;light2<=3'b010;state2<=s2;end

8

s2:begin num2<=green2;light2<=3'b001;state2<=s3;end s3:begin num2<=yellow2;light2<=3'b010;state2<=s0;end default:light2<=3'b100; endcase end else

begin //倒数计时 if(num2>0)

if(num2[3:0]==0) begin

num2[3:0]<=4'b1001; num2[7:4]<=num2[7:4]-1; end

else num2[3:0]<=num2[3:0]-1; if(num2==1) tim2<=0; end end else begin

tim2<=0;

state2<=2'b00; light2<=3'b010; end end

always @(posedge clk) begin //数码管译码显示 case(num1[3:0])

4'b0000: out1<=~7'b0111111; //0 ,3F 4'b0001: out1<=~7'b0000110; //1 ,06 4'b0010: out1<=~7'b1011011; //2 ,5B 4'b0011: out1<=~7'b1001111; //3 ,4F 4'b0100: out1<=~7'b1100110; //4 ,66 4'b0101: out1<=~7'b1101101; //5 ,6D 4'b0110: out1<=~7'b1111101; //6 ,7D 4'b0111: out1<=~7'b0000111; //7 ,07 4'b1000: out1<=~7'b1111111; //8, 7F 4'b1001: out1<=~7'b1101111; //9, 6F default: out1<=~7'b0111111; //0 ,3F endcase end

always @(posedge clk)

9

begin //数码管译码显示 case(num1[7:4])

4'b0000: out2<=~7'b0111111; //0 ,3F 4'b0001: out2<=~7'b0000110; //1 ,06 4'b0010: out2<=~7'b1011011; //2 ,5B 4'b0011: out2<=~7'b1001111; //3 ,4F 4'b0100: out2<=~7'b1100110; //4 ,66 4'b0101: out2<=~7'b1101101; //5 ,6D 4'b0110: out2<=~7'b1111101; //6 ,7D 4'b0111: out2<=~7'b0000111; //7 ,07 4'b1000: out2<=~7'b1111111; //8, 7F 4'b1001: out2<=~7'b1101111; //9, 6F default: out2<=~7'b0111111; //0 ,3F endcase end

always @(posedge clk) begin //数码管译码显示 case(num2[3:0])

4'b0000: out3<=~7'b0111111; //0 ,3F 4'b0001: out3<=~7'b0000110; //1 ,06 4'b0010: out3<=~7'b1011011; //2 ,5B 4'b0011: out3<=~7'b1001111; //3 ,4F 4'b0100: out3<=~7'b1100110; //4 ,66 4'b0101: out3<=~7'b1101101; //5 ,6D 4'b0110: out3<=~7'b1111101; //6 ,7D 4'b0111: out3<=~7'b0000111; //7 ,07 4'b1000: out3<=~7'b1111111; //8, 7F 4'b1001: out3<=~7'b1101111; //9, 6F default: out3<=~7'b0111111; //0 ,3F endcase end

always @(posedge clk) begin //数码管译码显示 case(num2[7:4])

4'b0000: out4<=~7'b0111111; //0 ,3F 4'b0001: out4<=~7'b0000110; //1 ,06 4'b0010: out4<=~7'b1011011; //2 ,5B 4'b0011: out4<=~7'b1001111; //3 ,4F 4'b0100: out4<=~7'b1100110; //4 ,66 4'b0101: out4<=~7'b1101101; //5 ,6D 4'b0110: out4<=~7'b1111101; //6 ,7D 4'b0111: out4<=~7'b0000111; //7 ,07

10

百度搜索“77cn”或“免费范文网”即可找到本站免费阅读全部范文。收藏本站方便下次阅读，免费范文网，提供经典小说综合文库交通灯设计 verilog(2)在线全文阅读。