数字电路与逻辑设计实验(4)

BEGIN

IF(clk'EVENT AND clk='1')THEN IF(cnt=5)THEN cnt<=0; ELSE cnt<=cnt+1; END IF; END IF;

END PROCESS change; P0:PROCESS(clk1) BEGIN

IF(clk1'EVENT AND clk1='1')THEN IF(cnt1=5)THEN cnt1<=0; ELSE cnt1<=cnt1+1; END IF; END IF; END PROCESS p0; P1:PROCESS(cnt,cnt1) BEGIN

IF(clear='0')THEN l<=\ ELSE

CASE cnt+cnt1 IS

WHEN 0=>l<=\ WHEN 1=>l<=\ WHEN 2=>l<=\ WHEN 3=>l<=\ WHEN 4=>l<=\

WHEN 5=>l<=\ WHEN 6=>l<=\ WHEN 7=>l<=\ WHEN 8=>l<=\ WHEN 9=>l<=\ WHEN 10=>l<=\ WHEN 11=>l<=\ WHEN OTHERS =>l<=\ END CASE; END IF; END PROCESS p1; guan<=q_temp; p2:PROCESS(cnt) BEGIN

IF(clear='0')THEN c<=\ ELSE CASE cnt IS

WHEN 0=>c<=\ WHEN 1=>c<=\ WHEN 2=>c<=\ WHEN 3=>c<=\ WHEN 4=>c<=\ WHEN 5=>c<=\ WHEN OTHERS =>c<=\ END CASE; END IF; END PROCESS p2;

xuan<=count; END zuo;

（3） 亮了又熄灭：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY bianhua IS PORT(

clk,clear:IN STD_LOGIC;

guan:out STD_LOGIC_VECTOR (6 downto 0); xuan:OUT STD_LOGIC_VECTOR(5 downto 0) );

end bianhua;

ARCHITECTURE wei OF bianhua IS signal tmp:integer range 0 to 5; signal w:integer range 0 to 5; signal s:integer range 0 to 10; signal k:integer range 0 to 1; signal o:integer range 0 to 6; signal p:integer range -1 to 1; signal clko:std_logic_vector(0 to 5); BEGIN

process(clear,clk) begin

if clear='0' then tmp<=0; w<=0;

s<=0; k<=0; o<=6; p<=-1;

elsif (clk'event and clk='1')then if tmp=5 then tmp<=0; w<=w+1; else

tmp<=tmp+1; end if; if w=6 then w<=0; end if;

for i in 0 to 5 loop if k=0 then if tmp>=o then clko(i)<='1'; elsif tmp

if (5-tmp)>=o then clko(i)<='1'; elsif tmp