AT24C164-10PU-2.7中文资料(9)

元器件交易网

AT24C164

Device Addressing

The AT24C164 requires an 8-bit device address word following a start condition toenable the chip for read or write operations (see Figure 7 on page 10). The most signifi-cant bit must be a one followed by the A2, A1 and A0 device select bits (the A1 bit mustbe the compliment of the A1 input pin signal). The next 3 bits are used for memory blockaddressing and select one of the eight 256 x 8 memory blocks. These bits should beconsidered the three most significant bits of the data word address. The eighth bit of thedevice address is the read/write select bit. A read operation is selected if this bit is highor a write operation is selected if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare isnot made, the chip will return to a standby state.

Write Operations

BYTE WRITE: A write operation requires an 8-bit data word address following thedevice address word and acknowledgment. Upon receipt of this address, the EEPROMwill again respond with a zero and then clock in the first 8-bit data word. Followingreceipt of the 8-bit data word, the EEPROM will output a zero and the addressingdevice, such as a microcontroller, must terminate the write sequence with a stop condi-tion. At this time the EEPROM enters an internally-timed write cycle, tWR, to thenonvolatile memory. All inputs are disabled during this write cycle and the EEPROM willnot respond until the write is complete (see Figure 8 on page 11).

PAGE WRITE: The AT24C164 is capable of a 16-byte page write. A page write is initi-ated the same as a byte write, but the microcontroller does not send a stop conditionafter the first data word is clocked in. Instead, after the EEPROM acknowledges receiptof the first data word, the microcontroller can transmit up to fifteen more data words. TheEEPROM will respond with a zero after each data word received. The microcontrollermust terminate the page write sequence with a stop condition (see Figure 9 on page11).

The data word address lower 4 bits are internally incremented following the receipt ofeach data word. The higher data word address bits are not incremented retaining thememory page row location. When the word address, internally generated, reaches thepage boundary, the following byte is placed at the beginning of the same page. If morethan sixteen data words are transmitted to the EEPROM, the data word address will “rollover” and previous data will be overwritten.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and theEEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-ing a start condition followed by the device address word. The read/write bit isrepresentative of the operation desired. Only if the internal write cycle has completedwill the EEPROM respond with a zero allowing the read or write sequence to continue.

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0105J–SEEPR–12/06

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