MAX1310ECM中文资料(14)

with ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

Figure 4. Typical Unipolar Operating Circuit

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with ±10V, ±5V, and 0 to +5V Analog Input Ranges

acquisition time must be limited to 1ms. Accuracy withconversion times longer than 1ms cannot be guaran-teed due to capacitor droop in the input circuitry.

Due to the analog input resistive divider formed by R1and R2 in Figure 5, any significant analog input sourceresistance (RSOURCE) results in gain error. Further-more, RSOURCEcauses distortion due to nonlinear analog input currents. Limit RSOURCEto a maximum of 100 .

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

Selecting an Input Buffer

To improve the input signal bandwidth under AC condi-tions, drive the input with a wideband buffer (>50MHz)that can drive the ADC’s input capacitance (15pF) andsettle quickly. For example, the MAX4431 or theMAX4265 can be used for the 0 to +5V unipolar devices,or the MAX4350 can be used for ±5V bipolar inputs.

Most applications require an input buffer to achieve 12-bitaccuracy. Although slew rate and bandwidth are impor-tant, the most critical input buffer specification is settlingtime. The simultaneous sampling of multiple channelsrequires an acquisition time of 100ns. At the beginning ofthe acquisition, the ADC internal sampling capacitor arrayconnects to the analog inputs, causing some distur-bance. Ensure the amplifier is capable of settling to atleast 12-bit accuracy during this interval. Use a low-noise,low-distortion, wideband amplifier that settles quickly andis stable with the ADC’s 15pF input capacitance.

See the Maxim website at for appli-cation notes on how to choose the optimum bufferamplifier for your ADC application.

Input Bandwidth

The input-tracking circuitry has a 20MHz small-signalbandwidth, making it possible to digitize high-speedtransient events and measure periodic signals withbandwidths exceeding the ADC’s sampling rate byusing undersampling techniques. To avoid high-fre-quency signals being aliased into the frequency bandof interest, anti-alias filtering is recommended.

Input Range and Protection

The MAX1304/MAX1305/MAX1306 provide a 0 to +5Vinput voltage range with fault protection of ±6V. TheMAX1308/MAX1309/MAX1310 provide a ±5V input volt-age range with fault protection of ±16.5V. TheMAX1312/MAX1313/MAX1314 provide a ±10V inputvoltage range with fault protection of ±16.5V. Figure 5shows the single-channel equivalent input circuit.

Figure 5. Single-Channel, Equivalent Analog Input T/H Circuit

Analog Inputs

Track and Hold (T/H)

To preserve phase information across the multichannelMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314, all input channels have dedicated T/H ampli-fiers. Figure 5 shows the equivalent analog input T/Hcircuit for one channel.

The input T/H circuit is controlled by the CONVST input.When CONVST is low, the T/H circuit tracks the analoginput. When CONVST is high the T/H circuit holds theanalog input. The rising edge of CONVST is the analoginput sampling instant. There is an aperture delay (tAD)of 8ns and a 50psRMSaperture jitter (tAJ). The aperturedelay of each dedicated T/H input is matched within100ps of each other.

To settle the charge on CSAMPLEto 12-bit accuracy,use a minimum acquisition time (tACQ) of 100ns.Therefore, CONVST must be low for at least 100ns.Although longer acquisition times allow the analog inputto settle to its final value more accurately, the maximum

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with ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

Data Throughput

The data throughput (fTH) of the MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 is a functionof the clock speed (fCLK). In internal clock mode, fCLK=15MHz (typ). In external clock mode, 100kHz ≤fCLK≤20MHz. When reading during conversion (Figures 7 and8), calculate fTHas follows:

fTH=

tACQ+tQUIET

1

+

fCLK

Clock Modes

The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 provide a 15MHz internal conversion clock.Alternatively, an external clock can be used.

Internal Clock

Internal clock mode frees the microprocessor from theburden of running the ADC conversion clock. For inter-nal clock operation, connect INTCLK/EXTCLKto AVDDand connect CLK to DGND. Note that INTCLK/EXTCLKis referenced to AVDD, not DVDD.

External Clock

For external clock operation, connect INTCLK/EXTCLKto AGND and connect an external clock source to CLK.Note that INTCLK/EXTCLKis referenced to AVDD, notDVDD. The external clock frequency can be up to20MHz. Linearity is not guaranteed with clock frequen-cies below 100kHz due to droop in the T/H circuits.

where N is the number of active channels and tQUIETisthe period of bus inactivity before the rising edge ofCONVST. See the Starting a Conversion section formore information.

Table 1 uses the above equation and shows the totalthroughput as a function of the number of channelsselected for conversion.

Table 1. Throughput vs. Channels Sampled: f

= 15MHz, t= 100ns, t= 50ns

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