EN71PL032A0-70CWP中文资料(4)

Pin Description

A20–A0 DQ15–DQ0 CE1#f CE1#ps CE2ps OE# WE# RY/BY# UB# LB# RESET# WP#/ACC VCCf VCCps VSS NC

21 Address Inputs (Common) 16 Data Inputs/Outputs (Common) Chip Enable 1 (Flash) Chip Enable 1 (pSRAM) Chip Enable 2 (pSRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output (Flash) Upper Byte Control (pSRAM) Lower Byte Control (pSRAM)

Hardware Reset Pin, Active Low (Flash) Hardware Write Protect/Acceleration Pin (Flash) Flash 3.0 volt-only single power supply pSRAM Power Supply Device Ground (Common) Pin Not Connected Internally

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